1. Field of the Invention
The present invention relates to a switching circuit having an output voltage varying among a reference voltage (ground) and a negative voltage.
2. Discussion of the Related Art
In non volatile memory devices of EEPROM and Flash EEPROM type, it is possible to write, to read and to electrically erase the elementary memory cells that compose them: particularly, the erasing of the Flash EEPROM memories consists in an operation that lowers the value of the threshold voltage of the memory cells extracting the negative charge stored in the floating gate.
Such operation of erasing can be effected through two fundamental techniques.
In the first one of these two techniques an electric field is produced, necessary to the erasing operation, bringing the source terminal of the memory cells to a high positive voltage value, keeping the control gate electrode grounded and the drain electrode disconnected.
The problems connected with the use of this first erasing technique concern the high voltage value applied to the source electrode of the cells: on one hand this provokes a strong absorption of current due to the breakdown current, that doesn't contribute to the erase efficiency. On the other hand, in low supply voltage devices, where the voltages of value higher than the supply voltage must be generated by boosting circuits, an undesired source of consumption is introduced.
In the second technique, instead, the source electrode of the memory cells is brought to a voltage level near the supply voltage and a negative voltage value is applied to the control gate electrode, still keeping the drain electrode disconnected.
For instance, with reference to the FIG. 1, a Flash EEPROM memory is schematically represented, or a sector of a Flash EEPROM memory in the case the memory includes more selectively addressable sectors, including memory cells 1, constituted by N-channel floating-gate MOS transistors, conventionally arranged in rows WL0-WLn ("word lines") and columns BL0-BLm ("bit lines") to form a matrix. The rows of the matrix are accessible through a row decoder ROW.sub.13 DEC that receives and decodes row address signals RADD. Such decoder includes a plurality of final driving stages for driving the rows, each one substantially constituted by a CMOS inverter 2 fed by a supply voltage VPCX and a voltage node RDS that can be selectively connected to the ground of the integrated circuit or to a line carrying a negative voltage value.
Node RDS is connected to ground in the case of reading and programming, as well as during erasing, if the shown sector must not be erased. Node RDS is instead connected to the negative voltage line for the operation of erasing of the sector. In this last case, the inputs of all the final inverters 2 are brought to the voltage VPCX.
The problems concerning this second erasing technique of the memory cells are mainly related to the above-described difficulty in handling negative voltages. Since integrated circuits are generally realized with CMOS technology, it may not be possible to apply negative voltages of desired value to the source or drain electrodes of the N-channel MOSFETs, without forward biasing the source/substrate or drain/substrate junctions, since the substrate of the integrated circuit is connected to ground.
Such problem is solved using a CMOS technology that allows isolation of the substrate of the device, necessarily connected to ground, from the bulk electrode of the N-channel MOSFETs.
In FIG. 2, for instance, the section of an N-channel MOS transistor is shown, the transistor realized in triple well technology, and in FIG. 3 the circuit symbol that represents such transistor is shown. In FIG. 2 a deep P type substrate 3 is connected to ground. An N type tub 4 is formed in the substrate 3, and the tub 4 is connected to the supply voltage VDD; inside tub 4, another tub 5 of the P type is located, with two N+ doped zones corresponding to the source and drain electrodes; the electrode of the tub 5 is connected to the source electrode. Both the substrate 3 and the tubs 4 and 5 are connected to the respective external electrodes through contact regions that have a higher doping.
With the triple well technology the N-channel MOSFET has the N type tub 4 such that by applying the positive supply voltage VDD to this region and when negative voltages to the source electrode, connected to the bulk electrode 5 of the same transistor, it is possible to reverse bias all the parasitic junctions existing in the structure.
Nevertheless, even the use of N-channel MOSFETs in triple well technology doesn't solve the problems related to a correct control of the same, i.e., to the voltages to be applied to the gate electrode of such MOSFETs to guarantee that they are turned off: in fact, if a negative voltage value is applied to the source electrode of such a transistor, to be able to turn it off, it is not enough to apply to the gate electrode a voltage equal to ground.
In view of the state of the art described, an object of the present invention is to provide a switching circuit capable of alternatively providing, at the output, a voltage equal to the ground or to a negative value, without incurring in the above mentioned drawbacks.